1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device in which a dielectric film located between electrodes of a capacitor is made of high permittivity dielectric material as well as a method of manufacturing the same.
2. Description of the Related Art
In recent years, demands for semiconductor memory devices have been rapidly increased owing to remarkable spread of information equipments such as computers. In connection with function, such devices have been demanded that have a large scale storage capacity and can operate at a high speed. In compliance with these demands, technologies have been developed for improving degree of integration, responsiveness and reliability of the semiconductor memory devices.
DRAMs (Dynamic Random Access Memories) have been known as a kind of semiconductor memory devices which can perform random input and output of storage information. The DRAM is formed of a memory cell array, which is a storage region storing a large number of memory information, and a peripheral circuitry required for external input and output.
A structure of the DRAM will be described below.
FIG. 18 is a block diagram showing a structure of a conventional DRAM. Referring to FIG. 18, a DRAM 350 includes a memory cell array 351, a row and column address buffer 352, a row decoder 353, a column decoder 354, a sense refresh amplifier 355, a data-in buffer 356, a data-out buffer 357 and a clock generator 358.
Memory cell array 351 serves to store data signals of memory information. Row and column address buffer 352 serves to receive an externally applied address buffer signal used for selecting a memory cell which forms a unit memory circuit. Row decoder 353 and column decoder 354 decode the address buffer signal to designate the memory cell. Sense refresh amplifier 355 serves to amplify and read the signal stored in the designated memory cell. Data-in buffer 356 and data-out buffer 357 serve to input and output the data, respectively. Clock generator 358 serves to generate a clock signal.
In the semiconductor chip of the DRAM thus structured, memory cell array 351 occupies a large area. Memory cell array 351 is formed of a plurality of memory cells which are disposed in a matrix form and each is operable to store the unit memory information. Thus, in general, the memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto. This memory cell is well known as a memory cell of one-transistor and one-capacitor type. The memory cell thus constructed has a simple structure, so that the degree of integration of the memory cell array can be improved readily and thus the memory cells have been widely used in the DRAM of a large capacity.
The memory cell of the DRAM can be classified into several types according to the structure of the capacitor. In a stacked type capacitor among them, an opposition area of electrodes of the capacitor can be increased readily. Therefore, a sufficient capacitor capacitance can be readily ensured even if elements of the semiconductor device are miniaturized to a high extent for improving the degree of integration. By this reason, the stacked type capacitors have been widely used in accordance with high integration of the semiconductor device.
FIG. 19 shows a sectional structure of a DRAM provided with a stacked type capacitor in the prior art. Referring to FIG. 19, a silicon substrate 331 is provided at its surface with an isolating oxide film 333 for electrically isolating elements from each other. A channel stopper region 335 is formed at a region under isolating oxide film 333. Isolating oxide film 333 and channel stopper region 335 electrically isolate a portion of the surface of silicon substrate 331, at which a memory cell of the DRAM is formed. Memory cell includes one transfer gate transistor 330 and one capacitor 320.
Transfer gate transistor 330 includes a gate oxide film 321, a gate electrode 323 and a pair of source/drain regions 325. Source/drain regions 325 are formed at the surface of silicon substrate 331 with a predetermined space between each other. Source/drain regions 325 have an LDD (Lightly Doped Drain) structure. Thus, each of source/drain regions 325 is formed of a two-layer structure including a relatively lightly doped impurity region 325a and a relatively heavily doped impurity region 325b. Gate electrode 323 is formed on a region located between source/drain regions 325 with gate oxide film 321 therebetween. The surface of gate electrode 323 is covered with an insulating film 327.
There is formed an insulating film 329 which covers transfer gate transistor 330 and partially exposes the surfaces of source/drain regions 325. Capacitor 320 is in contact with one of source/drain regions 325 not covered by insulating film 329.
Capacitor 320 has a lower electrode layer 313, a capacitor insulating layer 315 and an upper electrode layer 317. Lower electrode layer (storage node) 313 is in contact with the surface of one of source/drain regions 325 and extends over insulating film 329. Capacitor insulating layer 315 mainly made of silicon oxide covers the surface of lower electrode layer 313. Upper electrode layer (cell plate) 317 covers lower electrode layer 313 with capacitor insulating layer 315 therebetween. Electric charges are accumulated in an opposition region through which lower electrode layer 313 and upper electrode layer 317 at both sides of capacitor insulating layer 315 oppose to each other.
An interlayer insulating film 301 covering capacitor 320 is formed over the whole surface of silicon substrate 331. Interlayer insulating film 301 is provided with a contact hole 301a. Contact hole 301a reaches the surface of the other of source/drain regions 325. A bit line 337 is formed on interlayer insulating film 301 and is in contact with source/drain region 325 through contact hole 301a.
Bit line 337 includes a polycrystalline silicon layer 337a and a tungsten silicide layer 337b. More specifically, polycrystalline silicon layer 337a and tungsten silicide layer 337b are successively deposited to form bit line 337. Bit line 337 is covered with an insulating film 319.
The memory cell having the stacked type capacitor shown in FIG. 19 is suitable to high integration owing to the structural features described above.
If the DRAM is integrated to a higher degree, further reduction of the memory cell size is inevitably required. In accordance with reduction of the memory cell size, a planar area occupied by the capacitor is also reduced. If the occupied planar area is reduced as described above, an area of surface region of lower electrode layer 313 decreases substantially in proportion to the above planar reduction, and accordingly, the opposition area of electrodes of capacitor 320 also decreases. Thus, the quantity of charges accumulated in the capacitor (i.e., the quantity of charges accumulated in the memory cell of one bit) decreases. If the quantity of charges accumulated in the memory cell of one bit decreases below a predetermined value, operation of the DRAM as the storage region becomes unstable, resulting in lower reliability.
In order to prevent the instability in operation of DRAM, it is necessary to increase the capacitance of capacitor while maintaining the occupied planar area within a limited value. In order to increase the capacitor capacitance, such measures as (1) reduction of a thickness of the capacitor insulating layer and (2) increase of the dielectric constant of the capacitor insulating layer have been studied.
In connection with the reduction of the thickness of the capacitor insulating layer at the aforementioned item (1), the thickness has been generally reduced to a limit as long as a silicon oxide film is used as the capacitor insulating layer. Therefore, it is necessary to provide a capacitor of a complicated form such as a cylindrical form or a fin-like form in order to increase the capacitor capacitance using the capacitor insulating layer made of a silicon oxide film. However, the capacitor having such a complicated form requires an extremely complicated manufacturing process.
Accordingly, technologies are now being developed extensively in connection with increase of the capacitor dielectric constant at the above item (2). Increase of the dielectric constant of the capacitor insulating layer can be achieved by employing the capacitor insulating layer made of material having a high dielectric constant, i.e., so-called high permittivity dielectric material. This high permittivity dielectric material generally has a dielectric constant several times to several hundred times as large as that of a silicon oxide film. Therefore, by using the capacitor insulating layer made of the high permittivity dielectric material, the capacitance can be readily increased while maintaining a simple form of the capacitor.
Material referred to as the high permittivity dielectric material includes tantalum oxide (Ta.sub.2 O.sub.5), lead titanate zirconate (PZT), lanthan-lead titanate zirconate (PLZT), strontium titanate (STO), barium titanate (BTO).
Description will be made on a memory cell structure of the DRAM having the capacitor employing the capacitor insulating layer made of high permittivity dielectric material, with reference to the drawings showing a conventional semiconductor device.
FIG. 20 is a cross section schematically showing a structure of the conventional semiconductor device. Referring to FIG. 20, a plurality of memory cells of a DRAM are formed at a region in a silicon substrate 31 isolated by isolating oxide films 33 and channel stopper regions 35. Each memory cell is a memory cell of one-transistor and one-capacitor type having a transfer gate transistor 30 and a capacitor 420.
Each transfer gate transistor 30 has a gate oxide film 21, a gate electrode 23 and a pair of source/drain regions 25. Source/drain regions 25 are formed at the surface of silicon substrate 31 with a predetermined space between each other. Source/drain regions 25 have an LDD (Lightly Doped Drain) structure. Thus, each of source/drain regions 25 is formed of a two-layer structure including a relatively lightly doped impurity region 25a and a relatively heavily doped impurity region 25b. Gate electrode 23 is formed on a region located between paired source/drain regions 25 with gate oxide film 21 therebetween. The surface of gate electrode 23 is covered with an insulating film 27.
A bit line 37 extends on insulating film 27 and is in contact with one of the source/drain regions 25 forming the transfer gate transistor 30. Bit line 37 and transfer gate transistor 30 are covered with an interlayer insulating film 401 which is made of a silicon oxide film and is formed on the whole surface of silicon substrate 31. Bit line 37 thus covered with interlayer insulating film 401 is in the form of a buried bit line.
Interlayer insulating film 401 is provided with contact holes 401a. Each contact hole 401a reaches a surface of the other of source/drain regions 25. Each contact hole 401a is filled with a plug layer 409a. Plug layer 409a is made of polycrystalline silicon doped with impurity (which will also be referred to as "doped polycrystalline silicon").
The top surface of plug layer 409a is recessed or receded by a distance r from the top surface of interlayer insulating film 401. Thus, the top surface of plug layer 409a forms a recess of a size r with respect to the top surface of interlayer insulating film 401. Capacitor 420 is formed such that it electrically connects with source/drain region 25 through plug layer 409a.
Capacitor 420 has a lower electrode layer 413, a capacitor insulating layer 415 and an upper electrode layer 417. Capacitor insulating layer 415 of capacitor 420 is made of the high permittivity dielectric material such as PZT, as already described. The PZT and PLZT exhibit the largest dielectric constant when layers of them are formed on platinum (Pt). Therefore, lower electrode layer 413 is made of platinum in many cases.
Lower electrode layer 413 is electrically connected to plug layer 409a via barrier layer 411, e.g., made of titanium (Ti) and extends on the surface of interlayer insulating film 401. Barrier layer 411 prevents diffusion of impurity contained in plug layer 409a into lower electrode layer 413, and also serves to improve adhesion between lower electrode layer 413 and interlayer insulating film. Capacitor insulating layer 415 made of high permittivity dielectric material covers the surface of lower electrode layer 413. Upper electrode layer 417 covers lower electrode layer 413 with capacitor insulating layer 415 therebetween.
Upper electrode layer 417 may be made of platinum or doped polycrystalline silicon. Capacitor 420 is covered with an insulating film 419.
Now, a method of manufacturing the conventional semiconductor device will be described below.
FIGS. 21 to 30 are schematic cross sections showing a process of manufacturing the conventional semiconductor device in accordance with the order of steps. Referring first to FIG. 21, isolating oxide film 33 is formed at the surface of silicon substrate 31, for example, by an LOCOS (Local Oxidation of Silicon) method. At this step, channel stopper region 35 is formed at a region under the isolating oxide film 33.
Gate electrode 23 is formed on the surface of silicon substrate 31 with gate oxide film 21 therebetween. Using gate electrode 23 and others as a mask, ion implantation is carried out to form relatively lightly doped impurity regions 25. Insulating film 27 is formed to cover gate electrode 23. Using insulating film 27 and others as a mask, ion implantation is carried out to form relatively heavily doped impurity regions 25b. Lightly and heavily doped impurity regions 25a and 25b form source/drain regions 25. In this manner, transfer gate transistor 30 is formed.
Buried bit line 37 is formed such that it extends on insulating film 27 and is in contact with one of source/drain regions 25. A silicon oxide film 401b is formed on the whole surface of silicon substrate 31 by, for example, a CVD (Chemical Vapor Deposition) method so that it covers buried bit line 37 and transfer gate transistor 30. A resist film 401c for forming a flat surface is formed on the surface of silicon oxide film 401b. Resist film 401c may be formed by applying an SOG (Spin On Glass) film. Then, resist film 401c and silicon oxide film 401b are etched back up to a position indicated by dotted line.
Referring to FIG. 22, by this etchback, silicon oxide film 401 having a substantially flat surface is completed.
Referring to FIG. 23, photoresist is applied to the whole surface of silicon oxide film 401, and is patterned into an intended configuration by, for example, exposure. By this patterning, resist pattern 441 having hole patterns 441a located above source/drain regions 25 is completed.
Referring to FIG. 24, anisotropic etching is effected on silicon oxide film 401, using this resist pattern 441 as a mask. By the etching contact holes 401a are formed, which partially expose the surfaces of source/drain regions 25, in silicon oxide film 401. Thereafter, resist pattern 441 is removed.
Referring to FIG. 25, doped polycrystalline silicon film 409 having a film thickness from 5000 to 8000 .ANG. and filling contact hole 401 is formed by the CVD method on the whole surface of silicon oxide film 401. Etchback is effected on doped polycrystalline silicon film 409 to expose at least the surface of silicon oxide film 401.
Referring to FIG. 26, the aforementioned etchback is carried out such that about 20% to 30% of the film thickness of doped polycrystalline silicon film 409 is over-etched for completely removing etching residue on stepped portions (not shown) of the surface of silicon oxide film 401. Owing to the over-etching and the accompanied loading effect, doped polycrystalline silicon film 409a is recessed by a considerable amount (size r) from the surface of silicon oxide film 401.
Silicon oxide film 401 is hardly removed by the above etch-back because it has an etching selectivity higher than that of doped polycrystalline silicon film 409.
Referring to FIG. 27, barrier layer 411, e.g., of titanium and platinum layer 413 are successively deposited by the sputtering method on the surface including the surfaces of plug layers 409a recessed by the size r.
Referring to FIG. 28, resist pattern 443 patterned into intended configuration is formed on a part of the surface of platinum layer 413. Using resist pattern 443 as a mask, platinum layer 413 and barrier layer 411 are successively etched and removed. Thereby, lower electrode layer 413 made of platinum is completed. Thereafter, resist pattern 443 is removed.
Referring to FIG. 29, sputtering is performed to form capacitor insulating layer 415 made of high permittivity dielectric material such as PZT to cover the surfaces of lower electrode layers 413.
Referring to FIG. 30, sputtering is performed to form upper electrode layer 417, made of e.g., platinum to cover the surface of lower electrode layer 413 with capacitor insulating layer 415 therebetween. Thereby, capacitor 420 including lower electrode layer 413, capacitor insulating layer 415 and upper electrode layer 417, is completed. Insulating film 419 covering capacitor 420 is formed by the CVD method.
The conventional semiconductor device using the capacitor insulating layer made of high permittivity dielectric material is structured and manufactured as described above. Further, the capacitor capacitance can be readily increased while maintaining a simple shape of the capacitor as described above, so that such a capacitor is a promising candidate for highly integrated storage element such as 256M DRAM.
However, the conventional semiconductor device and the method of manufacturing the same suffer from following three problems.
First problem is that the anti-leak characteristics and breakdown voltage characteristics between lower electrode layer 413 and upper electrode layer 417 forming capacitor 420 are degraded.
In the process of etching back doped polycrystalline silicon film 409 shown in FIGS. 25 and 26, over-etching is effected on the doped polycrystalline silicon film 409 for completely removing the etching residue at the top surface of silicon oxide film 401. Doped polycrystalline silicon film 409 may be etched by the RIE of the parallel plate type under the etching conditions suitable to mass production (e.g., with gas system of SF.sub.6, flow rate of SF.sub.6 of 100 sccm, gas pressure of 500 mTorr, RF power of 200 W, time from 1 to 2 minutes and input power of 0.25 W/cm.sup.2). In this case, the etching selectivity of doped polycrystalline silicon film 409 with respect to silicon oxide film 401 is from 10 to 20. Thus, doped polycrystalline silicon film 409 can be etched very easily, while silicon oxide film 401 is hardly etched.
When doped polycrystalline silicon film 409 is etched to a certain extent so that the top surface of silicon oxide film 401 is exposed, the exposed portions of the doped polycrystalline silicon 409 remains only in the contact holes 401a. When the exposed area of the film to be etched, i.e., doped polycrystalline silicon film 409 remarkably decreases as described above, the etching rate of the film to be etched increases due to a so-called loading effect.
Due to the synergetic effect of the over-etching of doped polycrystalline silicon film 409 and the loading effect, each plug layer 409a has the top surface which is recessed by a certain size into contact hole 401a. Thus, the recess is formed in contact hole 401a. Platinum layer 413 and capacitor insulating layer 415 made of high permittivity dielectric material are formed on the structure including the recesses by the method such as the sputtering method of which step coverage is poor as shown in FIGS. 27 and 29, so that capacitor insulating layer 415 has thin portions located on stepped portions of platinum layer 413.
FIG. 31 is an enlarged fragmentary cross section showing the recess (portion P) shown in FIG. 20. Referring to FIG. 31, capacitor insulating layer 415 has a thin portion or, in the worst case, discontinuous portion at the lower end (portion R) of the recess. If the film thickness of capacitor insulating layer 415 is reduced, a leak current between lower electrode layer 413 and upper electrode layer 417 increases, so that it is difficult to obtain a predetermined breakdown voltage. Thus, good breakdown voltage characteristics and good anti-leak characteristics cannot be obtained between lower electrode layer 413 and upper electrode layer 417. If capacitor insulating layer 415 is disconnected, upper electrode layer 417 and lower electrode layer 413 are directly connected together, so that the structure cannot function as a capacitor.
The second problem is that the structure of the conventional semiconductor device can hardly improve the degree of integration.
In general, if the DRAM is integrated to a higher degree, a memory cell size is inevitably reduced. This reduction of memory cell size reduces a pitch between word lines. More specifically, as shown in FIG. 20, distance L.sub.0 of 0.6 .mu.m between word lines (gate electrodes) 23 has been studied. A minimum allowable open diameter L.sub.F of contact hole 401a is limited to 0.4 .mu.m by the photolithography. Under these conditions, distance L.sub.G between contact hole 401a and word line 23 is 0.1 .mu.m. Thus, 0.1 .mu.m, which is the distance L.sub.G between word line 23 and contact hole 401a, is a value of overlap margin of the mask for forming contact hole 401a.
However, the mask overlapping accuracy at the mass production level in the photolithography is about 0.18 .mu.m. Therefore, the overlap margin under the above conditions may cause plug layer 409a to be in contact with word line 23.
FIGS. 32 to 34 are schematic cross sections showing the process, in accordance with the order of steps, by which the plug layer and the word lines are formed to be in contact with each other. Referring first to FIG. 32, in order to form the contact hole reaching source/drain region 25 in silicon oxide film 401, resist pattern 441 is first formed on silicon oxide film 401. In this step, a center (alternate long and short dash line N--N) of hole pattern 441a in resist pattern 441 may cause a lateral shift L.sub.I within a range of 0.18 .mu.m with respect to an alignment center (alternate long and two short dashes line M--M). If this shift L.sub.I exceeds the aforementioned overlap margin of 0.1 .mu.m, the state shown in FIG. 33 occurs.
Referring to FIG. 33, if contact hole 401a is formed in silicon oxide film 401 with the mask formed of resist pattern 441 of which shift L.sub.I is 0.1 .mu.m or more, the side surface of word line 23 is exposed on the sidewall of contact hole 401a. When resist pattern 441 is removed from the structure in this state, and contact hole 401a is filled with plug layer 409a, plug layer 409a and word line 23 are short-circuited as shown in FIG. 34.
Under the above conditions, plug layer 409a may be connected to channel stopper region 35.
FIGS. 35 and 36 are schematic cross sections showing the state in which the plug layer and the channel cut region are connected together, in accordance with the order of steps. Referring first to FIG. 32, if the center (alternate long and short dash line N--N) of hole pattern 441a is shifted leftward by a distance of 0.18 .mu.m from the alignment center (alternate long and two short dashes line), the structure shown in FIG. 35 will be formed.
Referring to FIG. 35, a part of the surface of channel stopper region 35 is exposed at the bottom of contact hole 401a. Subsequently, resist pattern 441 is removed, and contact hole 401a is filled with plug layer 409a, so that plug layer 409a and channel stopper region 35 are connected together as shown in FIG. 36.
From the above description, it is apparent that distances such as the size L.sub.G between contact hole 401a and word line 23 must be large in order to prevent connection between plug layer 409a and word line 23 and connection between plug layer 409a and channel stopper region 35. Therefore, the distance L.sub.0 is necessarily large, which increases a planar area occupied by memory cells.
Further, if contact hole 401a is formed with a shifted or dislocated mask, contact hole 401a may protrude from a region at which lower electrode layer 413 is formed.
FIGS. 37A and 37B are schematic plan views showing a state where the contact hole protrudes from the formation region of the lower electrode layer. Referring to FIG. 37A, it has been studied to from contact hole 401a, which has a width L.sub.Q of 1 .mu.m and a length L.sub.R of 0.5 .mu.m, above lower electrode layer 413. An open diameter L.sub.F of contact hole 401a is 0.4 .mu.m due to the limit by the photolithography. Therefore, if contact hole 401a is dislocated in the direction indicated by arrow P due to the shift of mask, it is very likely that contact hole 401a protrudes from the formation region of lower electrode layer 413 as shown at FIG. 37B.
In general, the size of lower electrode layer 413 is set small so as to comply with high integration. Nevertheless, as shown at FIG. 37B, contact hole 401a protrudes from the formation region of lower electrode layer 413, so that the protrusion impedes higher integration.
Accordingly, the conventional semiconductor device is not suitable to higher integration.
Third problem is that the breakdown voltage characteristics of interlayer insulating film 401 is degraded.
The conventional semiconductor device uses the silicon oxide film as interlayer insulating film 401. The etching selectivity of silicon oxide film is small similarly to titanium forming barrier layer 411. Therefore, when lower electrode layer 413 and barrier layer 411 are etched and removed by the process shown in FIG. 28, interlayer insulating film 401 is also etched and removed.
FIG. 38 is a schematic cross section showing a state where the interlayer insulating film is removed by the etching simultaneously with the patterning of the lower electrode layer and others. Referring to FIG. 38, if the interlayer insulating film 401 is selectively removed by etching together with the intended layers, the film thickness S of silicon oxide film 401 above buried bit line 37 is reduced, or, in the worst case, buried bit line 37 is exposed. If the film thickness S of silicon oxide film 401 above buried bit line 37 is reduced, the insulating property and breakdown voltage between the capacitor, which will be formed later, and buried bit line will be degraded.